Non-volatile semiconductor memory cells using a charge storage region to store charges and memory arrays of such non-volatile memory cells in a semiconductor substrate are well known in the art. The charge storage region or charge storage sites are electrically insulated from and capacitively coupled to surrounding electrodes through surrounding insulators. Typically, the memory cell state is altered by introducing electron charges onto the charge storage region in a program operation or by removing electron charges off the charge storage region in an erase operation. The amounts of charges retained in the charge storage region define the states of a memory cell. Typically, the states thus defined can be either two levels or more than two levels (for multi-level states storage). The memory cell of such memory cells have been of the single-gate type, split gate type, or stacked gate type, or a combination thereof.
Well-known mechanisms such as channel hot electron injection (CHEI), source-side injection (SSI), Fowler-Nordheim tunneling (FN), impacted channel hot electrons (ICHE), and Band-to-Band Tunneling (BTBT) induced hot electron injection can be used to alter the states of such cells in program operation. Examples on employing such mechanisms for memory operations can be seen in U.S. Pat. Nos. 4,698,787, 5,029,130, 5,792,670, 6,144,581 and 5,966,329 for CHEI, SSI, FN, ICHE, and BTBT mechanisms, respectively.
For re-programmability, the cells need be erased by performing the erase operation. All the cells in the patents mentioned above are erased by using Fowler-Nordheim tunneling mechanism. Similar technique has been widely employed in other types of memory cells (for example, U.S. Pat. Nos. 6,631,087, 5,604,700, and 5,465,231).
The present invention can best be understood with an understanding of how the memory cells in prior art are constructed and how they are operated for erase operation. Thus a short introduction is presented to describe the prior art cell structures and the cell operations.
FIG. 1A illustrates a cross sectional view for a portion of cell structure 100a of the prior arts. The cell 100a comprises a floating gate (FG) 14, a body 16, a source 18, and a drain 20 with a channel 22 of the body 16 defined therebetween. Both the source 18 and the drain 20 are assumed of n-type conductivity. The body 16 is assumed of p-type conductivity and is in a well 24 of same conductivity (“p-Well”). FG 14 is disposed over and insulated from the channel 22 by a layer of storage insulator 26. There are shown electrons 30 stored on FG 14 to represent the cell in the programmed state.
The erase operation on prior arts cell is done by utilizing Fowler-Nordheim tunneling mechanism to remove electrons 30 off FG 14 typically along one of the trajectories shown in dotted-lines 32a, 32b, and 32c. The trajectories 32a and 32b show electrons 30 transporting to the source 18 and to the channel 22, respectively. The electrons can be removed along trajectory 32c if adding a tunneling capacitor 28 to the cell 100a. Proper voltages and bias polarity are applied to the cell for the erase operation. For example, to remove electrons 30 along the trajectory 32c, the voltage VTUN at tunneling capacitor 28 is sufficiently positive with respect to the voltages at the source (VS), drain (VD) or body (VB).
FIG. 1B illustrates a cross sectional view for another cell structure 100b of the prior arts. The cell 100b is identical in all respects except one the same as that of FIG. 1A. The difference is that an additional element of control gate 34 is disposed over and insulated from the FG 14 by a coupling insulator 36. The erase operation of this cell is done by utilizing Fowler-Nordheim tunneling to remove electrons 30 off FG 14 along one or all of the trajectories shown in dotted-lines 32a, and 32b. Proper voltages and bias polarity are applied to the cell. For example, to remove electrons 30 along the trajectory 32a and 32b, the voltage VCG at control gate 34 is sufficiently negative with respect to VS, VD or VB. Typical voltages for erasing the memory cell are: VCG=−10V, VS=+10V, and VB=+10V. The drain 20 is left open during the erase operation.
In erasing these types of memory cells with Fowler-Nordheim tunneling mechanism, a high voltage (typically ranging from 9 to 20V) is required to perform the operation in order to set a desired logic states (e.g. a “0” state) to the cells. To support the memory cell operation, infrastructure for on-chip high voltage generation is thus essential and has become an essential block in memories and products. The infrastructure involves separate sets of transistors used for handling high voltages and typically required adding at least 5 extra masks to a conventional CMOS technology. Therefore, it complicates process technology for manufacturing the memories. Further, the FN mechanism unavoidably introduces stress field in the range of about 10 MV/cm to the surrounding insulator, and results in charge leakage and retention failure even when memory cells are under a low field condition. It is believed that the high voltage demands stringent control on the quality of the surrounding insulators. The memories operated under the mechanism thus are vulnerable to manufacturing and reliability problems.
U.S. Pat. No. 6,348,711 taught an EEPROM memory cell structure and operation method. The cell is erased by injecting holes into the floating gate using Band-to-Band Tunneling (BTBT) mechanism. Similar technique has been widely employed in other types of memory cells (for example, U.S. Pat. Nos. 6,617,637, 6,906,953 and 6,934,193). Such erase method is believe suffered from the problems of low injection efficiency (Here, the term “injection efficiency” is defined as the ratio of the number of charge carriers entering into FG to the number of charge carriers supplied by the source).
The erase operation for cells 100a and 100b can alternately be performed by removing electrons via non-electrical means, such as application of ultraviolet (UV) light treatment to memory cells. Examples on UV treatment can be seen in U.S. Pat. Nos. 6,882,574 and 6,885,587. One of the major problems for UV treatment is that the erase operation requires erasure of the entire memory device by application of UV light even erase is made for changing the content of only a single byte. The memory device has to be removed from the circuit board in order to perform UV treatment for the erase operation. The process is tedious and adds inconvenience in product applications.
The present invention solves these problems by providing cell structure and operation methods. The erase operation of the present cell permits the voltage drop across the storage insulator be confined in range less than about 3 V. Therefore, it avoids the high field stress on the insulator and hence the reliability problem. Other advantages, objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.